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Abstract
In this paper, a single-precision floating-point FFT twiddle factor (TF) implementation is proposed. The architecture is based on the Adaptive Angle Recoding CORDIC (AARC) algorithm. The TF design was built and verified on Altera Stratix IV FPGA chip and 65nm SOTB synthesis. The FPGA implementation had 103.9 MHz maximum frequency, throughput result of 16.966 Mega-Sample per second (MSps), and resources utilization of 7.747 ALUTs and 625 registers. On the other hand, the SOTB synthesis has 16.858 standard cells on an area of 298x291 μm2, 166 MHz maximum frequency, and the speed of 27.107 MSps. The accuracy results were 1.133E-10 Mean-Square-Error (MSE) and about 26 part-per-million (ppm) maximum error.
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Article Details
Issue: Vol 1 No T4 (2017)
Page No.: 187-196
Published: Dec 31, 2017
Section: Original Research
DOI: https://doi.org/10.32508/stdjns.v1iT4.468
Copyright Info
Copyright: The Authors. This is an open access article distributed under the terms of the Creative Commons Attribution License CC-BY 4.0., which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
How to Cite
Vo, T., Truong, Q., Hoang, T., & Le, H. (2017). An efficient floating-point FFT twiddle factor implementation based on adaptive angle recoding CORDIC algorithm. Science & Technology Development Journal: Natural Sciences, 1(T4), 187-196. https://doi.org/https://doi.org/10.32508/stdjns.v1iT4.468
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